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| micron parallel nor flash embedded memory M29DW256G x16 multiple bank, page, dual boot 3v supply flash memory features ? supply voltage C v cc = 2.7C3.6v (program, erase, read) C v ccq = 1.65C3.6v (i/o buffers) C v pph = 9v for fast program (optional) ? asynchronous random/page read C page size: 8 words C page access: 25ns, 30ns C random access: 70ns, 80ns ? fast program commands: 32-word ? enhanced buffered program commands: 256-word ? program time C 16s per byte/word typ C chip program time: 10 s with v pph and 16s with- out v pph ? memory organization C quadruple bank memory array: 32mb + 96mb + 96mb + 32mb with parameter blocks at top and bottom C dual operation: program/erase in one bank while reading in any other bank ? program/erase controller C embedded word program algorithms ? program/erase suspend and resume capability C read from any block during a program sus- pend operation C read or program another block during an erase suspend operation ? unlock bypass, block erase, chip erase, write to buf- fer, and enhanced buffer program commands C fast buffered/batch programming C fast block/chip erase ? v pp /wp# pin for fast program and write C protects the four outermost parameter blocks ? software protection C volatile protection C nonvolatile protection C password protection ? extended memory block C programmed or locked at the factory or by the customer C 128 word factory locked and 128 word customer lockable ? common flash interface C 64-bit security code ? low power consumption: standby and automatic mode ? 100,000 minimum program/erase cycles per block ? data retention: 20 years (typ) ? fortified bga, tbga, and tsop packages ? green packages available C rohs-compliant C halogen-free ? automotive certified parts available C automotive device grade: temperature C40c to +85c (automotive grade certified) ? root part number C M29DW256G ? device code C 227eh + 223ch + 2202h 256mb: 3v embedded parallel nor flash features pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
part numbering information available with extended memory block prelocked by micron. devices are shipped from the factory with memory content bits erased to 1. for available options, such as packages or high/low protection, or for further information, contact your micron sales representative. part numbers can be verified at www.micron.com . feature and specifica- tion comparison by device type is available at www.micron.com/products . contact the factory for devices not found. table 1: part number information part number category category details notes device type m29 architecture d = dual operation operating voltage w = vcc = 2.7 to 3.6v device function 256g = 256mb (x16) page, dual boot speed 70 = 70ns 1, 2 7a = 70ns 1, 2 package nf = 56-pin tsop, 14mm x 20mm, lead-free, halogen-free, rohs-compliant za = 64-pin tbga, 10mm x 13mm, lead-free, halogen-free, rohs-compliant zs = 64-pin fortified bga, 11mm x 13mm, lead-free, halogen-free, rohs-compliant temperature range 1 = 0 to 70c 6 = C40c to +85c shipping options e = rohs-compliant package, standard packing f = rohs-compliant package, tape and reel packing notes: 1. 80ns if vccq = 1.65v to vcc. 2. automotive certified C40c to +85c, available only with option 6. 256mb: 3v embedded parallel nor flash features pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. contents description ...................................................................................................................................................... 7 signals ......................................................................................................................................................... 8 signal assignments ........................................................................................................................................... 9 signal descriptions ......................................................................................................................................... 11 memory organization .................................................................................................................................... 13 memory configuration ............................................................................................................................... 13 block addresses and protection groups ....................................................................................................... 14 bus operations ............................................................................................................................................... 18 read .......................................................................................................................................................... 18 write .......................................................................................................................................................... 18 standby and automatic standby ................................................................................................................. 18 output disable ........................................................................................................................................... 19 reset .......................................................................................................................................................... 19 registers ........................................................................................................................................................ 20 status register ............................................................................................................................................ 20 lock register .............................................................................................................................................. 25 standard command definitions C address-data cycles .................................................................................... 27 read and auto select operations .............................................................................................................. 30 read/reset command ............................................................................................................................ 30 read cfi command .................................................................................................................................. 30 unlock bypass read cfi command ....................................................................................................... 30 auto select command ........................................................................................................................... 30 bypass operations .......................................................................................................................................... 32 unlock bypass command ...................................................................................................................... 32 unlock bypass reset command ............................................................................................................ 32 program operations ....................................................................................................................................... 33 program command ................................................................................................................................ 33 unlock bypass program command ..................................................................................................... 33 write to buffer program command .................................................................................................. 33 unlock bypass write to buffer program command ....................................................................... 36 write to buffer program confirm command .................................................................................. 36 buffered program abort and reset command ................................................................................ 36 program suspend command ................................................................................................................ 36 program resume command .................................................................................................................. 37 write to buffer program suspend command .................................................................................. 37 write to buffer program resume command .................................................................................... 38 enter enhanced buffered command ................................................................................................ 38 enhanced buffered program command ........................................................................................... 38 enhanced buffered program abort reset command .................................................................... 39 exit enhanced buffered program command ................................................................................... 41 erase operations ............................................................................................................................................ 42 chip erase command .............................................................................................................................. 42 unlock bypass chip erase command ................................................................................................... 42 block erase command ........................................................................................................................... 42 unlock bypass block erase command ................................................................................................ 43 erase suspend command ....................................................................................................................... 43 erase resume command ........................................................................................................................ 44 block protection command definitions C address-data cycles ........................................................................ 45 protection operations .................................................................................................................................... 47 lock register commands ...................................................................................................................... 47 256mb: 3v embedded parallel nor flash features pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. password protection commands ....................................................................................................... 47 nonvolatile protection commands .................................................................................................. 48 nonvolatile protection bit lock bit commands ............................................................................ 49 volatile protection commands .......................................................................................................... 50 extended memory block commands .................................................................................................. 50 exit protection command .................................................................................................................... 51 device protection ........................................................................................................................................... 52 hardware protection .................................................................................................................................. 52 software protection .................................................................................................................................... 52 volatile protection mode ............................................................................................................................. 53 nonvolatile protection mode ...................................................................................................................... 53 password protection mode .......................................................................................................................... 54 dual operations and multiple bank architecture ............................................................................................. 56 common flash interface ................................................................................................................................ 58 power-up and reset characteristics ................................................................................................................ 61 absolute ratings and operating conditions ..................................................................................................... 63 dc characteristics .......................................................................................................................................... 65 read ac characteristics .................................................................................................................................. 66 write ac characteristics ................................................................................................................................. 68 accelerated program, data polling/toggle ac characteristics ........................................................................... 72 program/erase characteristics ........................................................................................................................ 74 package dimensions ....................................................................................................................................... 75 revision history ............................................................................................................................................. 78 rev. a C 10/12 ............................................................................................................................................. 78 256mb: 3v embedded parallel nor flash features pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. list of figures figure 1: logic diagram ................................................................................................................................... 8 figure 2: 56-pin tsop (top view) .................................................................................................................... 9 figure 3: 64-pin fortified bga and 64-pin tbga ............................................................................................. 10 figure 4: block addresses .............................................................................................................................. 13 figure 5: data polling flowchart .................................................................................................................... 22 figure 6: toggle bit flowchart ........................................................................................................................ 23 figure 7: status register polling flowchart ..................................................................................................... 24 figure 8: lock register program flowchart ..................................................................................................... 26 figure 9: write to buffer program flowchart ........................................................................................ 35 figure 10: enhanced buffered program flowchart ............................................................................... 40 figure 11: program/erase nonvolatile protection bit algorithm ...................................................................... 49 figure 12: software protection scheme .......................................................................................................... 55 figure 13: power-up timing .......................................................................................................................... 61 figure 14: reset ac timing C no program/erase operation in progress ...................................................... 62 figure 15: reset ac timing during program/erase operation .................................................................... 62 figure 16: ac measurement load circuit ....................................................................................................... 64 figure 17: ac measurement i/o waveform ..................................................................................................... 64 figure 18: random read ac timing ............................................................................................................... 66 figure 19: page read ac timing ..................................................................................................................... 67 figure 20: we#-controlled program ac timing .............................................................................................. 69 figure 21: ce#-controlled program ac timing ............................................................................................... 71 figure 22: accelerated program ac timing ..................................................................................................... 72 figure 23: data polling ac timing .................................................................................................................. 73 figure 24: toggle/alternative toggle bit polling ac timing .............................................................................. 73 figure 25: 56-pin tsop C 14mm x 20mm ........................................................................................................ 75 figure 26: 64-pin tbga C 10mm x 13mm ........................................................................................................ 76 figure 27: 64-ball fortified bga C 11mm x 13mm ........................................................................................... 77 256mb: 3v embedded parallel nor flash features pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. list of tables table 1: part number information ................................................................................................................... 2 table 2: signal names ...................................................................................................................................... 8 table 3: signal descriptions ........................................................................................................................... 11 table 4: bank architecture ............................................................................................................................. 13 table 5: bank a ............................................................................................................................................. 14 table 6: bank b ............................................................................................................................................. 14 table 7: bank c ............................................................................................................................................. 16 table 8: bank d ............................................................................................................................................. 17 table 9: bus operations ................................................................................................................................. 18 table 10: status register bit definitions ......................................................................................................... 20 table 11: operations and corresponding bit settings ...................................................................................... 21 table 12: lock register bit definitions ............................................................................................................ 25 table 13: block protection status ................................................................................................................... 25 table 14: standard command definitions C address-data cycles, 16-bit ......................................................... 27 table 15: read electronic signature, auto select mode and programmer method ............................................. 31 table 16: block protection (16-bit mode) ........................................................................................................ 31 table 17: block protection command definitions C address-data cycles, 16-bit .............................................. 45 table 18: extended memory block address and data ...................................................................................... 50 table 19: v pp /wp# functions ......................................................................................................................... 52 table 20: dual operations allowed in other banks ......................................................................................... 56 table 21: dual operations allowed in same bank ........................................................................................... 57 table 22: query structure overview ............................................................................................................... 58 table 23: cfi query identification string ........................................................................................................ 58 table 24: cfi query system interface information .......................................................................................... 59 table 25: device geometry definition ............................................................................................................ 59 table 26: primary algorithm-specific extended query table ........................................................................... 60 table 27: security code area .......................................................................................................................... 60 table 28: power-up wait timing specifications .............................................................................................. 61 table 29: reset ac specifications ................................................................................................................... 62 table 30: absolute maximum/minimum ratings ............................................................................................ 63 table 31: operating conditions ...................................................................................................................... 63 table 32: input/output capacitance 1 ............................................................................................................. 64 table 33: dc current characteristics .............................................................................................................. 65 table 34: dc voltage characteristics .............................................................................................................. 65 table 35: read ac characteristics .................................................................................................................. 66 table 36: we#-controlled write ac characteristics ......................................................................................... 68 table 37: ce#-controlled write ac characteristics ......................................................................................... 70 table 38: accelerated program and data polling/data toggle ac characteristics .............................................. 72 table 39: program/erase characteristics ........................................................................................................ 74 256mb: 3v embedded parallel nor flash features pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. description the M29DW256G is a 256mb (16mb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (2.7 to 3.6 v) supply. at power-up the memory defaults to its read mode. the M29DW256G features an asymmetrical block architecture, with 8 parameter and 126 main blocks, divided into four banks, a, b, c and d, providing multiple bank opera- tions. while programming or erasing in one bank, read operations are possible in any other bank. four of the parameter blocks are at the top of the memory address space, and four are at the bottom. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any er- ror conditions identified. the command set required to control the memory is consis- tent with jedec standards. chip enable, output enable and write enable signals control the bus operations of the memory. they allow simple connection to most microprocessors, often without addi- tional logic. the device supports asynchronous random read and page read from all blocks of the memory array. the device also features a write to buffer program capability that im- proves the programming throughput by programming 32 words in one instance. the enhanced buffered program feature is also available to speed up programming through- put, allowing 256 words to be programmed at once. the v pp /wp# signal can be used to enable faster programming of the device. the M29DW256G has one extra 256-word extended block that can be accessed using a dedicated command: 128-word factory locked and 128-word customer lockable. the extended block can be protected and so is useful for storing security information. how- ever the protection is irreversible; once protected the protection cannot be undone. the device features different levels of hardware and software block protection to avoid unwanted program or erase (modify): ? hardware protection: v pp /wp# provides hardware protection on four outermost pa- rameter blocks (two at the top and two at the bottom of the address space) ? software protection: volatile protection, nonvolatile protection, password protection the memory is offered in tsop56 (14mm x 20mm), tbga64 (10mm x 13mm, 1mm pitch), and fbga (11mm x 13mm) packages. the memory is delivered with all the bits erased (set to 1). 256mb: 3v embedded parallel nor flash description pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. signals table 2: signal names name description direction a[23:0] address inputs inputs dq[15:0] data inputs/outputs i/o ce# chip enable input oe# output enable input we# write enable input rst# reset input ry/by# ready/busy output output v ccq input/output buffer supply voltage supply v cc supply voltage supply v pp/ wp# v pp /write protect supply/input v ss ground C nc not connected C note: 1. 1 v pp /wp# may be left floating as it is internally connected to a pull-up resistor which enables program/erase operations. figure 1: logic diagram v cc v ccq a[23:0] we# v pp /wp# dq[15:0] v ss ce# oe# rst# nc ry/by# 256mb: 3v embedded parallel nor flash description pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. signal assignments figure 2: 56-pin tsop (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 v pp /wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 rfu rfu rfu rfu a16 rfu v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 rfu v ccq note: 1. a[23] = a[max]. 256mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 3: 64-pin fortified bga and 64-pin tbga a b c d e f g h a b c d e f g h 1 rfu rfu rfu rfu rfu v ccq rfu rfu 2 a3 a4 a2 a1 a0 ce# oe# v ss 3 a7 a17 a6 a5 d0 d8 d9 d1 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 5 we# rst# a21 a19 d5 d12 v cc d4 5 we# rst# a21 a19 d5 d12 v cc d4 6 a9 a8 a10 a11 d7 d14 d13 d6 6 a9 a8 a10 a11 d7 d14 d13 d6 7 a13 a12 a14 a15 a16 rfu d15 v ss 7 a13 a12 a14 a15 a16 rfu d15 v ss 8 rfu a22 a23 v ccq v ss rfu rfu rfu 8 rfu a22 a23 v ccq v ss rfu rfu rfu 3 a7 a17 a6 a5 d0 d8 d9 d1 2 a3 a4 a2 a1 a0 ce# oe# v ss 1 rfu rfu rfu rfu rfu v ccq rfu rfu top view C ball side down bottom view C ball side up note: 1. a[23] = a[max]. 256mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. signal descriptions the signal description table below is a comprehensive list of signals for this device fami- ly. all signals listed may not be supported on this device. see signal assignments for in- formation specific to this device. table 3: signal descriptions name type description a[max:0] input address: selects the cells in the array to access during read operations. during write oper- ations, they control the commands sent to the command interface of the program/erase con- troller. dq[15:0] i/o data i/o: outputs the data stored at the selected address during a read operation. during write operations, they represent the commands sent to the command interface of the inter- nal state machine. during write operations, bits dq[15:8] are not used. when reading the status register, these bits should be ignored. ce# input chip enable: activates the device, enabling read and write operations to be performed. when ce# is high, the device goes to standby and data outputs are at high-z. oe# input output enable: controls the bus read operation. we# input write enable: controls the bus write operation of the command interface. v pp /wp# input v pp /write protect: provides two functions. the v pph function enables the device to bypass unlock cycles and use an external high voltage power supply to reduce time required for program operations. second, when v pp /wp# is low, the four outermost blocks of the address space (two 32kw blocks at the top and two 32kw blocks at the bottom) are protected; program and erase operations are ignored and the blocks remain protected regardless of the block protection status or the rst# pin state. when v pp /wp# is high, the memory reverts to the previous pro- tection status for those blocks (refer to hardware protection and bypass operations for de- tails). rst# input reset: applies a hardware reset to the device, which is achieved by holding rst# low for at least t plpx. after rst# goes high, the device is ready for read and write operations (after t phel or t rhel, whichever occurs last). see reset ac specifications for more details. ry/by# output ready busy: open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations, ry/by# is low, and is high-z during read mode, auto select mode, and erase suspend mode. after a hard- ware reset, read and write operations cannot begin until ry/by# goes high-z (see reset ac specifications for more details). the use of an open-drain output enables the ry/by# pins from several devices to be connec- ted to a single pull-up resistor to v ccq . a low value will then indicate that one or more of the devices is busy. v cc supply supply voltage: provides the power supply for read, program, and erase operations. the command interface is disabled when v cc <= v lko . this prevents write operations from accidentally damaging the data during power-up, power-down, and power surges. if the pro- gram/erase controller is programming or erasing during this time, then the operation aborts and the contents being altered will be invalid. a 0.1 f capacitor should be connected between v cc and v ss to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations (see dc characteristics). 256mb: 3v embedded parallel nor flash signal descriptions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 3: signal descriptions (continued) name type description v ccq supply i/o supply voltage: provides the power supply to the i/o pins and enables all outputs to be powered independently from v cc . v ss supply ground: all v ss pins must be connected to the system ground. rfu C reserved for future use: rfus should be not connected. 256mb: 3v embedded parallel nor flash signal descriptions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. memory organization memory configuration the M29DW256G features an asymmetrical block architecture, with 8 parameter and 126 main blocks, divided into four banks providing multiple bank operations. four pa- rameter blocks are at the top of the memory address space, and four are at the bottom. table 4: bank architecture bank bank size parameter blocks main blocks number of blocks block size number of blocks block size a 32mb 4 32 kwords 15 128 kwords b 96mb 48 128 kwords c 96mb 48 128 kwords d 32mb 4 32 kwords 15 128 kwords figure 4: block addresses 128 kwords 800000h 81ffffh 128 kwords fc0000h fdffffh address lines a23-a0 128 kwords de0000h dfffffh total of 48 main blocks 128 kwords e00000h e1ffffh 32 kwords ff8000h ffffffh 32 kwords fe0000h fe7fffh total of 15 main blocks total of 4 parameter blocks bank c bank d 32 kwords 000000h 007fffh 128 kwords 1e0000h 1fffffh 32 kwords 018000h 01ffffh total of 4 parameter blocks 128 kwords 020000h 03ffffh 128 kwords 7e0000h 7fffffh 128 kwords 200000h 21ffffh total of 15 main blocks total of 48 main blocks bank b bank a 256mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. block addresses and protection groups table 5: bank a block protection group block size (kwords) 16-bit address range (in hexadecimal) 0 protection group 32 0000000 - 0007fff 1 protection group 32 0008000 - 000ffff 2 protection group 32 0010000 - 0017fff 3 protection group 32 0018000 - 001ffff 4 protection group 128 0020000 - 003ffff 5 protection group 128 0040000 - 005ffff 6 protection group 128 0060000 - 007ffff 7 protection group 128 0080000 - 009ffff 8 protection group 128 00a0000 - 00bffff 9 protection group 128 00c0000 - 00dffff 10 protection group 128 00e0000 - 00fffff 11 protection group 128 0100000 - 011ffff 12 protection group 128 0120000 - 013ffff 13 protection group 128 0140000 - 015ffff 14 protection group 128 0160000 - 017ffff 15 protection group 128 0180000 - 019ffff 16 protection group 128 01a0000 - 01bffff 17 protection group 128 01c0000 - 01dffff 18 protection group 128 01e0000 - 01fffff table 6: bank b block protection group block size (kwords) 16-bit address range (in hexadecimal) 19 protection group 128 0200000 - 021ffff 20 protection group 128 0220000 - 023ffff 21 protection group 128 0240000 - 025ffff 22 protection group 128 0260000 - 027ffff 23 protection group 128 0280000 - 029ffff 24 protection group 128 02a0000 - 02bffff 25 protection group 128 02c0000 - 02dffff 26 protection group 128 02e0000 - 02fffff 27 protection group 128 0300000 - 031ffff 28 protection group 128 0320000 - 033ffff 29 protection group 128 0340000 - 035ffff 30 protection group 128 0360000 - 037ffff 31 protection group 128 0380000 - 039ffff 32 protection group 128 03a0000 - 03bffff 256mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 6: bank b (continued) block protection group block size (kwords) 16-bit address range (in hexadecimal) 33 protection group 128 03c0000 - 03dffff 34 protection group 128 03e0000 - 03fffff 35 protection group 128 0400000 - 041ffff 36 protection group 128 0420000 - 043ffff 37 protection group 128 0440000 - 045ffff 38 protection group 128 0460000 - 047ffff 39 protection group 128 0480000 - 049ffff 40 protection group 128 04a0000 - 04bffff 41 protection group 128 04c0000 - 04dffff 42 protection group 128 04e0000 - 04fffff 43 protection group 128 0500000 - 051ffff 44 protection group 128 0520000 - 053ffff 45 protection group 128 0540000 - 055ffff 46 protection group 128 0560000 - 057ffff 47 protection group 128 0580000 - 059ffff 48 protection group 128 05a0000 - 05bffff 49 protection group 128 05c0000 - 05dffff 50 protection group 128 05e0000 - 05fffff 51 protection group 128 0600000 - 061ffff 52 protection group 128 0620000 - 063ffff 53 protection group 128 0640000 - 065ffff 54 protection group 128 0660000 - 067ffff 55 protection group 128 0680000 - 06fffff 56 protection group 128 06a0000 - 06bffff 57 protection group 128 06c0000 - 06dffff 58 protection group 128 06e0000 - 06fffff 59 protection group 128 0700000 - 071ffff 60 protection group 128 0720000 - 073ffff 61 protection group 128 0740000 - 075ffff 62 protection group 128 0760000 - 077ffff 63 protection group 128 0780000 - 079ffff 64 protection group 128 07a0000 - 07bffff 65 protection group 128 07c0000 - 07dffff 66 protection group 128 07e0000 - 07fffff 256mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 7: bank c block protection group block size (kwords) 16-bit address range (in hexadecimal) 67 protection group 128 0800000 - 081ffff 68 protection group 128 0820000 - 083ffff 69 protection group 128 0840000 - 085ffff 70 protection group 128 0860000 - 087ffff 71 protection group 128 0880000 - 089ffff 72 protection group 128 08a0000 - 08bffff 73 protection group 128 08c0000 - 08dffff 74 protection group 128 08e0000 - 08fffff 75 protection group 128 0900000 - 091ffff 76 protection group 128 0920000 - 093ffff 77 protection group 128 0940000 - 095ffff 78 protection group 128 0960000 - 097ffff 79 protection group 128 0980000 - 099ffff 80 protection group 128 09a0000 - 09bffff 81 protection group 128 09c0000 - 09dffff 82 protection group 128 09e0000 - 09fffff 83 protection group 128 0a00000 - 0a1ffff 84 protection group 128 0a20000 - 0a3ffff 85 protection group 128 0a40000 - 0a5ffff 86 protection group 128 0a60000 - 0a7ffff 87 protection group 128 0a80000 - 0a9ffff 88 protection group 128 0aa0000 - 0abffff 89 protection group 128 0ac0000 - 0adffff 90 protection group 128 0ae0000 - 0afffff 91 protection group 128 0b00000 - 0b1ffff 92 protection group 128 0b20000 - 0b3ffff 93 protection group 128 0b40000 - 0b5ffff 94 protection group 128 0b60000 - 0b7ffff 95 protection group 128 0b80000 - 0b9ffff 96 protection group 128 0ba0000 - 0bbffff 97 protection group 128 0bc0000 - 0bdffff 98 protection group 128 0be0000 - 0bfffff 99 protection group 128 0c00000 - 0c1ffff 100 protection group 128 0c20000 - 0c3ffff 101 protection group 128 0c40000 - 0c5ffff 102 protection group 128 0c60000 - 0c7ffff 103 protection group 128 0c80000 - 0cfffff 104 protection group 128 0ca0000 - 0cbffff 256mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 7: bank c (continued) block protection group block size (kwords) 16-bit address range (in hexadecimal) 105 protection group 128 0cc0000 - 0cdffff 106 protection group 128 0ce0000 - 0cfffff 107 protection group 128 0d00000 - 0d1ffff 108 protection group 128 0d20000 - 0d3ffff 109 protection group 128 0d40000 - 0d5ffff 110 protection group 128 0d60000 - 0d7ffff 111 protection group 128 0d80000 - 0d9ffff 112 protection group 128 0da0000 - 0dbffff 113 protection group 128 0dc0000 - 0ddffff 114 protection group 128 0de0000 - 0dfffff table 8: bank d block protection group block size (kwords) 16-bit address range (in hexadecimal) 115 protection group 128 e00000h-e1ffffh 116 protection group 128 e20000h-e3ffffh 117 protection group 128 e40000h-e5ffffh 118 protection group 128 e60000h-e7ffffh 119 protection group 128 e80000h-e9ffffh 120 protection group 128 ea0000h-ebffffh 121 protection group 128 ec0000h-edffffh 122 protection group 128 ee0000h-efffffh 123 protection group 128 f00000h-f1ffffh 124 protection group 128 f20000h-f3ffffh 125 protection group 128 f40000h-f5ffffh 126 protection group 128 f60000h-f7ffffh 127 protection group 128 f80000h-f9ffffh 128 protection group 128 fa0000h-fbffffh 129 protection group 128 fc0000h-fdffffh 130 protection group 32 fe0000h-fe7fffh 131 protection group 32 fe8000h-feffffh 132 protection group 32 ff0000h-ff7fffh 133 protection group 32 ff8000h-ffffffh 256mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. bus operations table 9: bus operations notes 1 through 3 apply to entire table operation ce# oe# we# rst# v pp /wp# address inputs data inputs/ outputs a[max], a[0] dq[15:0] read l l h h x cell address data output write l h l h x 4 command address data input 5 standby h x x h x x high-z output disable l h h h x x high-z reset x x x l x x high-z notes: 1. typical glitches of less than 5ns on ce#, we#, and rst# are ignored by the device and do not affect bus operations. 2. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 3. dual operations are possible with the device multiple bank architecture. while program- ming or erasing in one bank, read operations are possible in any of the other banks. write operations are only allowed in one bank at a time. 4. to write the four outermost parameter blocks (first two and the last two) v pp /wp# must be equal to v ih . 5. data input is required when issuing a command sequence or when performing data polling or block protection. read bus read operations read from the memory cells, registers, or cfi space. to accelerate the read operation, the memory array can be read in page mode where data is inter- nally read and stored in a page buffer. page size is 8 words and is addressed by address inputs a[2:0]. a valid bus read operation involves setting the desired address on the address inputs, taking ce# and oe# low, and holding we# high. the data i/os will output the value. (see ac characteristics for details about when the output becomes valid.) write bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the command interface on the falling edge of ce# or we#, whichever occurs last. the data i/os are latched by the command interface on the rising edge of ce# or we#, whichever occurs first. oe# must remain high during the entire bus write oper- ation. (see ac characteristics for timing requirement details.) standby and automatic standby driving ce# high in read mode causes the device to enter standby, and data i/os to be high-z. to reduce the supply current to the standby supply current (i cc2 ), ce# must be held within v cc 0.3v. (see dc characteristics.) 256mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. during program or erase operations the device will continue to use the program/ erase supply current (i cc3 ) until the operation completes. automatic standby allows the memory to achieve low power consumption during read mode. after a read operation, if cmos levels (vcc 0.3 v) are used to drive the bus and the bus is inactive for tavqv + 30ns or more, the memory enters automatic standby where the internal supply current is reduced to the standby supply current, icc2 (see dc characteristics). the data inputs/outputs still output data if a read operation is in progress. depending on load circuits connected with data bus, vccq, can have a null consumption when the memory enters automatic standby. output disable data i/os are high-z when oe# is high. reset during reset mode the device is deselected and the outputs are high-z. the device is in reset mode when rst# is low. the power consumption is reduced to the standby level, independently from ce#, oe#, or we# inputs. 256mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. registers status register table 10: status register bit definitions note 1 applies to entire table bit name settings description notes dq7 data polling bit 0 or 1, depending on operations monitors whether the program/erase controller has successful- ly completed its operation, or has responded to an erase sus- pend operation. 2, 3, 4 dq6 toggle bit toggles: 0 to 1; 1 to 0; and so on monitors whether the program/erase controller has successful- ly completed its operations, or has responded to an erase suspend operation. during a program/erase operation, dq6 toggles from 0 to 1, 1 to 0, and so on, with each succes- sive read operation from any address. 3, 4, 5 dq5 error bit 0 = success 1 = failure identifies errors detected by the program/erase controller. dq5 is set to 1 when a program, block erase, or chip erase op- eration fails to write the correct data to the memory. 4, 6 dq3 erase timer bit 0 = erase not in progress 1 = erase in progress identifies the start of program/erase controller operation dur- ing a block erase command. before the program/erase con- troller starts, this bit set to 0, and additional blocks to be erased can be written to the command interface. 4 dq2 alternative toggle bit toggles: 0 to 1; 1 to 0; and so on monitors the program/erase controller during erase opera- tions. during chip erase, block erase, and erase suspend operations, dq2 toggles from 0 to 1, 1 to 0, and so on, with each successive read operation from addresses within the blocks being erased. 3, 4 dq1 buffered program abort bit 1 = abort indicates a buffer program operation abort. the buffered program abort and reset command must be issued to re- turn the device to read mode (see write to buffer pro- gram command). notes: 1. the status register can be read during program, erase, or erase suspend operations; the read operation outputs data on dq[7:0]. 2. for a program operation in progress, dq7 outputs the complement of the bit being programmed. for a read operation from the address previously programmed success- fully, dq7 outputs existing dq7 data. for a read operation from addresses with blocks to be erased while an erase suspend operation is in progress, dq7 outputs 0; upon successful completion of the erase suspend operation, dq7 outputs 1. for an erase operation in progress, dq7 outputs 0; upon either operation's successful completion, dq7 outputs 1. 3. after successful completion of a program or erase operation, the device returns to read mode. 4. during erase suspend mode, read operations to addresses within blocks not being erased output memory array data as if in read mode. a protected block is treated the same as a block not being erased. see the toggle flowchart for more information. 5. during erase suspend mode, dq6 toggles when addressing a cell within a block being erased. the toggling stops when the program/erase controller has suspended the erase operation. see the toggle flowchart for more information. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. 6. when dq5 is set to 1, a read/reset command must be issued before any subsequent command. table 11: operations and corresponding bit settings note 1 applies to entire table operation address dq7 dq6 dq5 dq3 dq2 dq1 ry/by# notes program any address dq7# toggle 0 C no toggle 0 0 2 program during erase suspend any address dq7# toggle 0 C C C 0 enhanced buffered program entry any address C toggle 0 C C C 0 buffered program abort any address dq7# toggle 0 C C 1 0 2 program error any address dq7# toggle 1 C C C high-z chip erase any address 0 toggle 0 1 toggle C 0 block erase before time-out erasing block 0 toggle 0 0 toggle C 0 non-erasing block 0 toggle 0 0 no toggle C 0 block erase erasing block 0 toggle 0 1 toggle C 0 non-erasing block 0 toggle 0 1 no toggle C 0 erase suspend erasing block 1 no toggle 0 C toggle C high-z non-erasing block outputs memory array data as if in read mode C high-z block erase error good block address 0 toggle 1 1 no toggle C high-z faulty block address 0 toggle 1 1 toggle C high-z notes: 1. unspecified data bits should be ignored. 2. dq7# for buffer program is related to the last address location loaded. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 5: data polling flowchart start dq7 = data dq5 = 1 dq1 = 1 dq7 = data no no no no yes yes yes yes read dq7, dq5, and dq1 at valid address 1 read dq7 at valid address success failure 2 notes: 1. valid address is the address being programmed or an address within the block being erased. 2. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 6: toggle bit flowchart dq6 = toggle dq5 = 1 dq6 = toggle no no yes yes yes start read dq6 at valid address read dq6, dq5, and dq1 at valid address read dq6 (twice) at valid address success failure 1 dq1 = 1 no yes no note: 1. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 7: status register polling flowchart write to buffer program start dq7 = valid data dq5 = 1 yes no no yes yes dq6 = toggling yes no no no yes program operation no no dq6 = toggling no dq2 = toggling yes yes yes dq1 = 1 read 3 correct data? no yes read 1 read 2 read 2 read 3 device busy: repolling device busy: repolling read 3 program operation complete program operation failure write to buffer program abort timeout failure erase operation complete erase/suspend mode device error read2.dq6 = read3.dq6 read2.dq2 = read3.dq2 read1.dq6 = read2.dq6 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. lock register table 12: lock register bit definitions note 1 applies to entire table bit name settings description notes dq[15:5] rfu C reserved for future use 2 dq4 volatile lock boot bit programmable sets default values for volatile block protection; when this bit is programmed, blocks are protected at power-up. dq3 rfu C reserved for future use 2 dq2 password protection mode lock bit 0 = password protection mode enabled 1 = password protection mode disabled (default) places the device permanently in password protection mode. 3 dq1 nonvolatile protection mode lock bit 0 = nonvolatile protection mode enabled with pass- word protection mode permanently disabled 1 = nonvolatile protection mode enabled (default) places the device in nonvolatile protection mode with pass- word protection mode permanently disabled. when shipped from the factory, the device will operate in nonvolatile pro- tection mode, and the memory blocks are unprotected. 3 dq0 extended memory block protection bit 0 = protected 1 = unprotected (default) if the device is shipped with the extended memory block un- locked, the block can be protected by setting this bit to 0. the extended memory block protection status can be read in auto select mode by issuing an auto select command. it can also be read by applying v id to a9. notes: 1. the lock register is a 16-bit, one-time programmable register. 2. dq[15:5] and dq[3] are reserved and are set to a default value of 1. during program- ming, they must be held to 1. 3. the password protection mode lock bit and nonvolatile protection mode lock bit cannot both be programmed to 0. any attempt to program one while the other is programmed causes the operation to abort, and the device returns to read mode. the device is ship- ped from the factory with the default setting. table 13: block protection status nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 volatile protection bit 3 block protection status block protection status 0 0 x 01h block protected by nonvolatile protection bit; nonvolatile protection bit unchangeable. 0 1 1 00h block unprotected; nonvolatile protection bit unchangeable. 0 1 0 01h block protected by volatile protection bit; nonvolatile protec- tion bit unchangeable. 1 0 x 01h block protected by nonvolatile protection bit; nonvolatile protection bit changeable. 1 1 0 01h block protected by volatile protection bit; nonvolatile protec- tion bit changeable. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 13: block protection status (continued) nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 volatile protection bit 3 block protection status block protection status 1 1 1 00h block unprotected; nonvolatile protection bit changeable. notes: 1. nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked. 2. block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 3. block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. figure 8: lock register program flowchart start done? dq5 = 1 no no yes yes enter lock register command set address-data (unlock) cycle 1 address-data (unlock) cycle 2 address-data cycle 3 program lock register address-data cycle 1 address-data cycle 2 polling algorithm success: exit protection command set (returns to device read mode) address-data cycle 1 address-data cycle 2 failure: read/reset (returns device to read mode) notes: 1. each lock register bit can be programmed only once. 2. see the block protection command definitions table for address-data cycle details. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. standard command definitions C address-data cycles table 14: standard command definitions C address-data cycles, 16-bit note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d read and auto select operations read/reset (f0h) x16 x f0 555 aa 2aa 55 x f0 read cfi (98h) x16 bka 555 98 unlock bypass read cfi (98h) x16 bka 98 auto select (90h) x16 555 aa 2aa 55 bka 555 90 note 2 note 2 2, 3, 4 bypass operations unlock bypass (20h) x16 555 aa 2aa 55 555 20 unlock bypass reset (90h/00h) x16 x 90 x 00 program operations program (a0h) x16 555 aa 2aa 55 555 a0 pa pd unlock bypass program (a0h) x16 x a0 pa pd 5 write to buffer program (25h) x16 555 aa 2aa 55 bad 25 bad n pa pd 6, 7, 8 unlock bypass write to buffer program (25h) x16 bad 25 bad n pa pd 5 write to buffer program confirm (29h) x16 bad 29 buffered program abort and reset (f0h) x16 555 aa 2aa 55 555 f0 enter enhanced buffered program command set (38h) x16 555 aa 2aa 55 555 38 9 enhanced buffered program (33h) x16 bad 33 bad (00) data bad (01) data 9 256mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 14: standard command definitions C address-data cycles, 16-bit (continued) note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d enhanced buffered program confirm (29h) x16 bad (00) 29 exit enhanced buffered program command set (90h) x16 x 90 x 00 program suspend (b0h) x16 bka b0 program resume (30h) x16 bka 30 write to buffer pro- gram suspend (b0h) x16 bad b0 write to buffer pro- gram resume (30h) x16 bad 30 erase operations chip erase (80/10h) x16 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 unlock bypass chip erase (80/10h) x16 x 80 x 10 5 block erase (80/30h) x16 555 aa 2aa 55 555 80 555 aa 2aa 55 bad 30 10 unlock bypass block erase (80/30h) x16 x 80 bad 30 5 erase suspend (b0h) x16 bka b0 erase resume (30h) x16 bka 30 notes: 1. a = address; d = data; x = "don't care;" bka = bank address; bad = any address in the block; n = number of bytes to be programmed; pa = program address; pd = program data; gray shading = not applicable. all values in the table are hexadecimal. some com- mands require both a command code and subcode. 2. these cells represent read cycles (versus write cycles for the others). 3. auto select enables the device to read the manufacturer code, device code, block pro- tection status, and extended memory block protection indicator. 4. auto select addresses and data are specified in the electronic signature table and the extended memory block protection table. 5. for any unlock bypass erase/program command, the first two unlock cycles are unnecessary. 6. bad must be the same as the address loaded during the write to buffer program 3rd and 4th cycles. 7. write to buffer program operation: maximum cycles 36 (x16). unlock bypass write to buffer program operation: maximum cycles = 34 (x16). write to buffer 256mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. program operation: n + 1 = bytes to be programmed; maximum buffer size = 32 words (x16). 8. for x16, a[max:5] address pins should remain unchanged while a[4:0] pins are used to select a word within the n + 1 word page. 9. the following is content for address-data cycles 256 through 258: bad (fe) - data; bad (ff) - data; bad (00) - 29. 10. block erase address cycles can extend beyond six address-data cycles, depending on the number of blocks to erase. 256mb: 3v embedded parallel nor flash standard command definitions C address-data cycles pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. read and auto select operations read/reset command the device is in read mode after a reset or power-up. the read/reset (f0h) command returns the device to read mode and resets the errors in the status register. one or three bus write operations can be used to issue the read/reset command. to return the device to read mode, this command can be issued between bus write cycles before the start of a program or erase operation. if the read/reset com- mand is issued during the timeout of a block erase operation, the device requires up to 10 s to abort, during which time no valid data can be read. the read/reset command will not abort a program operation if executed while the device is in program suspend, or an erase operation if executed while the device is in erase suspend. read cfi command the read cfi (98h) command puts the device in read cfi mode and is only valid when the device is in read array or auto select mode. one bus write cycle is required to issue the command. once in read cfi mode, bus read operations will output data from the cfi memory area (refer to the common flash interface for details). a read/reset command must be issued to return the device to the previous mode (read array or auto select ). a sec- ond read/reset command is required to put the device in read array mode from auto select mode. unlock bypass read cfi command the unlock bypass read cfi (98h) command enables the device to read the cfi when the device is in the unlock bypass mode. once in read cfi mode, bus read operations will output data from the cfi memory area (refer to the common flash interface for details). a read/reset command must be issued to return the device to the previous mode (read array or auto select ). a sec- ond read/reset command is required to put the device in read array mode from auto select mode. auto select command at power-up or after a hardware reset, the device is in read mode. it can then be put in auto select mode by issuing an auto select (90h) command. auto select mode ena- bles the following device information to be read: ? electronic signature, which includes manufacturer and device code information as shown in the electronic signature tables. ? block protection, which includes the block protection status and extended memory block protection indicator, as shown in the block protection tables. for example, auto select mode can be used by the programming equipment to auto- matically match a device with the application code to be programmed. electronic signature or block protection information is read by executing a read opera- tion with control signals and addresses set, as shown in the read electronic signature 256mb: 3v embedded parallel nor flash read and auto select operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. tables or the block protection tables, respectively. if the block is protected, then 01h is output on data input/outputs dq0-dq7, otherwise 00h is output. three consecutive bus write operations are required to issue an auto select com- mand. the device remains in auto select mode until a read/reset or read cfi com- mand is issued. the device cannot enter auto select mode when a program or erase operation is in progress (ry/by# low) unless the respective operation is suspended by a program suspend or an erase suspend command. auto select mode is exited by performing a reset. the device returns to read mode un- less it entered auto select mode after an erase suspend or program suspend command, in which case it returns to erase or program suspend mode. table 15: read electronic signature, auto select mode and programmer method read cycle 1 e# g# w# address inputs data io a[23:10] a[9:8] a[7:5] a4 a3 a2 a1 a0 dq[15:0] manufacturer code v il v il v ih x x v il x v il v il v il v il 0020h device code (cycle 1) x v il v il v il v ih 227eh device code (cycle 2) v ih v ih v ih v il 223ch device code (cycle 3) v ih v ih v ih v ih 2202h note: 1. x = v il or v ih . table 16: block protection (16-bit mode) e# g# w# rst# v pp / wp# address inputs data io a[23:12] a[11:10] a9 a8 a7 a6 a[5:4] a[3:2] a1 a0 bits value operation: verify extended memory block indicator bit v il v il v ih v ih v ih bka x x x v il v il v il v il v ih v ih dq[15:8] 0 dq7 1 = factory locked dq6 1 = customer locked, 0 = customer lockable dq5 1 = reserved, 0 = standard dq[4:3] 00 = wp# protects 4 outermost blocks, 11 = no wp# protection (hardware write protection) dq[2:0] 0 operation: verify block protection status v il v il v ih v ih v ih bad x x x v il v il v il v il v ih v il 0000h (unprotected) 0001h (protected) note: 1. x = v il or v ih . bad any address in the block, bka bank address. 256mb: 3v embedded parallel nor flash read and auto select operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. bypass operations unlock bypass command the unlock bypass (20h) command is used to place the device in unlock bypass mode. three bus write operations are required to issue the unlock bypass com- mand. when the device enters unlock bypass mode, the two initial unlock cycles required for a standard program or erase operation are not needed, thus enabling faster total program or erase time. the unlock bypass command is used in conjunction with unlock bypass pro- gram or unlock bypass erase commands to program or erase the device faster than with standard program or erase commands. when the cycle time to the device is long, considerable time savings can be gained by using these commands. when in unlock bypass mode, only the following commands are valid: ? the unlock bypass program command can be issued to program addresses within the device. ? the unlock bypass block erase command can be issued to erase one or more memory blocks. ? the unlock bypass chip erase command can be issued to erase the whole mem- ory array. ? the unlock bypass write to buffer program command can be issued to speed up the programming operation. ? the unlock bypass cfi command can be issued to read the cfi when the memory is in unlock bypass mode ? the unlock bypass reset command can be issued to return the device to read mode. in unlock bypass mode, the device can be read as if in read mode. in addition to the unlock bypass command, when v pp /wp# is raised to v pph , the de- vice automatically enters unlock bypass mode. when v pp /wp# returns to v ih or v il , the device is no longer in unlock bypass mode and normal operation resumes. the transi- tions from v ih to v pph and from v pph to v ih must be slower than t vhvpp (see the accel- erated program, data polling/toggle ac characteristics). note: micron recommends the user enter and exit unlock bypass mode using enter unlock bypass and unlock bypass reset commands rather than raising v pp /wp# to v pph . v pp /wp# should never be raised to v pph from any mode except read mode; oth- erwise, the device may be left in an indeterminate state. unlock bypass reset command the unlock bypass reset (90/00h) command is used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the un- lock bypass reset command. the read/reset command does not exit from un- lock bypass mode. 256mb: 3v embedded parallel nor flash bypass operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. program operations program command the program (a0h) command can be used to program a value to one address in the memory array. the command requires four bus write operations, and the final write operation latches the address and data in the internal state machine and starts the pro- gram/erase controller. programming can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively. if the address falls in a protected block, the program command is ignored, and the data remains unchanged. the status register is not read, and no error condition is given. after programming has started, bus read operations output the status register content. a bus read operation from a bank different from the one whose blocks are being pro- grammed will output the memory array content. after the program operation has completed, the device returns to read mode, unless an error has occurred. when an error occurs, bus read operations to the device contin- ue to output the status register. a read/reset command must be issued to reset the error condition and return the device to read mode. the program command cannot change a bit set to 0 back to 1, and an attempt to do so is masked during a program operation. instead, an erase command must be used to set all bits in one memory block or in the entire memory from 0 to 1. the program operation is aborted by performing a reset or by powering-down the de- vice. in this case, data integrity cannot be ensured, and it is recommended that the aborted data be reprogrammed. unlock bypass program command when the device is in unlock bypass mode, the unlock bypass program (a0h) command can be used to program one address in the memory array. the command re- quires two bus write operations instead of four required by a standard program command; the final write operation latches the address and data and starts the pro- gram/erase controller (the standard program command requires four bus write op- erations). this unlock bypass program operation behaves identically to the pro- gram operation. the operation cannot be aborted. a bus read operation from the memory outputs the status register. a bus read operation from a bank different from the one whose blocks are being programmed will output the memory array content. write to buffer program command the write to buffer program (25h) command makes use of the 32-word program buffer to speed up programming. a maximum of 32 words can be loaded into the pro- gram buffer; each write buffer has the same a[23:5]. the write to buffer program command dramatically reduces system programming time compared to the standard non-buffered program command. when issuing a write to buffer program command, v pp /wp# can be either held high or raised to v pph . also, it can be held low if the block is not one of the four outer- 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. most blocks, depending on the part number. the following successive steps are re- quired to issue the write to buffer program command: first, two unlock cycles are issued. next, a third bus write cycle sets up the write to buffer program command. the set-up code can be addressed to any location within the targeted block. then, a fourth bus write cycle sets up the number of words to be programmed. value n is written to the same block address, where n + 1 is the number of words to be programmed. value n + 1 must not exceed the size of the pro- gram buffer, or the operation will abort. a fifth cycle loads the first address and data to be programmed. last, n bus write cycles load the address and data for each word into the program buffer. addresses must lie within the range from the start address +1 to the start address + (n - 1) . optimum programming performance and lower power usage are achieved by aligning the starting address at the beginning of a 32-word boundary; otherwise, programming time doubles. all addresses used in the operation must lie within the same page. to program the content of the program buffer, this command must be followed by a write to buffer program confirm command. if an address is written several times during a write to buffer program operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. invalid address combinations or the incorrect sequence of bus write cycles will abort the write to buffer program command. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during a write to buffer program operation. the write to buffer program command should not be used to change a bit set to 0 back to 1, and an attempt to do so is masked during the operation. rather than the write buffer program command, the erase command should be used to set memory bits from 0 to 1. the write to buffer program command can be suspended and then resumed by issuing a program suspend command and then a program resume command, respectively. after the write to buffer program operation has completed, the memory will re- turn to read mode, unless an error has occurred. when an error occurs, a read operation from the bank being programmed will continue to output the status register. a read op- eration from any bank other than the one being programmed will output the memory array content. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 9: write to buffer program flowchart abort write to buffer write buffer data, start address start x = n write n, 1 block address write to buffer and program aborted 2 write to a different block address x = 0 write next data, 3 program address pair write to buffer confirm, block address x = x - 1 yes no yes no dq7 = data no yes dq5 = 1 yes no dq1 = 1 no yes write to buffer command, block address read status register (dq1, dq5, dq7) at last loaded address dq7 = data 4 no yes check status register (dq5, dq7) at last loaded address fail or abort 5 end first three cycles of the write to buffer program command notes: 1. n + 1 is the number of addresses to be programmed. 2. the buffered program abort and reset command must be issued to return the de- vice to read mode. 3. when the block address is specified, any address in the selected block address space is acceptable. however, when loading program buffer address with data, all addresses must fall within the selected program buffer page. 4. dq7 must be checked because dq5 and dq7 may change simultaneously. 5. if this flowchart location is reached because dq5 = 1, then the write to buffer pro- gram command failed. if this flowchart location is reached because dq1 = 1, then the write to buffer program command aborted. in both cases, the appropriate reset command must be issued to return the device to read mode: a reset command if the operation failed; a write to buffer program abort and reset command if the op- eration aborted. 6. see the standard command definitions C address-data cycles, 16-bit table for details about the write to buffer program command sequence. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. unlock bypass write to buffer program command when the device is in unlock bypass mode, the unlock bypass write to buffer (25h) command can be used to program the device in fast program mode. the com- mand requires two bus write operations fewer than the standard write to buffer program command. the unlock bypass write to buffer program command behaves the same way as the write to buffer program command: the operation cannot be aborted, and a bus read operation from the memory outputs the status register. a bus read opera- tion from a bank different from the one whose blocks are being programmed will out- put the memory array content. the write to buffer program confirm command is used to confirm an un- lock bypass write to buffer program command and to program the n + 1 words loaded in the program buffer by this command. write to buffer program confirm command the write to buffer program confirm (29h) command is used to confirm a write to buffer program command and to program the n + 1 words loaded in the program buffer by this command. buffered program abort and reset command a buffered program abort and reset (f0h) command must be issued to abort the write to buffer program and enhanced buffered program operations and reset the device in read mode. the buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program in the write to buffer program command. ? write to an address in a different block than the one specified during the write buf- fer load command. ? write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq6 = toggle, and dq5 = 0 (all of which are status register bits). a buffered program abort and reset command sequence must be written to reset the device for the next operation. note: the full three-cycle buffered program abort and reset command se- quence is required when using buffer programming features in unlock bypass mode. program suspend command the program suspend (b0h) command can be used to interrupt a program opera- tion so that data can be read from any block. when the program suspend command is issued during a program operation, the device suspends the operation within the pro- gram suspend latency time and updates the status register bits. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. after the program operation has been suspended, data can be read from any address. however, data is invalid when read from an address where a program operation has been suspended. the program suspend command may also be issued during a program operation while an erase is suspended. in this case, data may be read from any address not in erase suspend or program suspend mode. to read from the extended memory block area (one-time programmable area), the enter/exit extended memory block command sequences must be issued. the system may also issue the auto select command sequence when the device is in program suspend mode. the system can read as many auto select codes as required. when the device exits auto select mode, the device reverts to program suspend mode and is ready for another valid operation. the program suspend operation is aborted by performing a device reset or power- down. in this case, data integrity cannot be ensured, and it is recommended that the aborted data be reprogrammed. program resume command the program resume (30h) command must be issued to exit a program suspend mode and resume a program operation. the controller can use dq7 or dq6 status bits to determine the status of the program operation. after a program resume command is issued, subsequent program resume commands are ignored. another program suspend command can be issued after the device has resumed program- ming. write to buffer program suspend command the write to buffer program suspend (b0h) command can be used to interrupt a write to buffer program operation so that data can be read from any block. when this command is issued, the device suspends the operation within the program suspend la- tency time and updates the status register bits. after the operation has been suspended, data can be read from any address. however, data is invalid when read from an address where a program operation has been suspen- ded. this command can also be issued during a write to buffer program operation while an erase is also suspended. in this case, data may be read from any address not in erase suspend or program suspend mode. to read from the extended memory block area (one-time programmable area), the enter/exit extended memory block command sequences must be issued. the system may also issue the auto select command sequence when the device is in write to buffer program suspend mode. the system can read as many auto select codes as required. when the device exits auto select mode, the device reverts to write to buffer program suspend mode and is ready for another valid operation. the program suspend operation is aborted by performing a device reset or power- down. in this case, data integrity cannot be ensured, and it is recommended that the aborted data be reprogrammed. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. write to buffer program resume command the write to buffer program resume (30h) command must be issued to exit a write to buffer program suspend mode and resume a write to buffer program operation. the controller can use dq7 or dq6 status bits to determine the status of the write to buffer program operation. after a write to buffer program re- sume command is issued, subsequent write to buffer program resume com- mands are ignored. another write to buffer program suspend command can be issued after the device has resumed programming. enter enhanced buffered command the enter enhanced buffered command is used to allow execution of the en- hanced buffered program commands. the device accepts only these following com- mands after the enter enhanced buffered command is issued; any other com- mand is ignored: ? enhanced buffered program (can be issued multiple times once the enter enhanced buffered command is executed) ? enhanced buffered program abort/reset ? exit enhanced buffered program to ensure the enter enhanced buffered command has completed successfully and the device is ready to receive one of the commands listed above, it is recommended to monitor toggle bit (dq6). enhanced buffered program command the enhanced buffered program command makes use of a 256-word write buf- fer to speed up programming. each write buffer has the same a23-a8 addresses. this command dramatically reduces system programming time compared to both the standard non-buffered program command and the write to buffer command. when issuing the enhanced buffered program command, the v pp /wp pin can be held high or raised to v pph (see program/erase characteristics). the following suc- cessive steps are required to issue the enhanced buffered program command: first, the enter enhanced buffered program command issued. next, one bus write cycle sets up the enhanced buffered program command. the set-up code can be addressed to any location within the targeted block. then, a second bus write cycle loads the first address and data to be programmed. there are a total of 256 address and data loading cycles. when the 256 words are loaded to the buffer, a third write cycle programs the content of the buffer. last, when the command completes, the exit enhanced buffered program command is issued. address/data cycles must be loaded in an increasing address order, from a[7:0] = 00000000 to a[7:0] = 11111111 until all 256 words are loaded. invalid address combina- tions or the incorrect sequence of bus write cycles will abort the enhanced buf- fered program command. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during an enhanced buffered program operation. an external 12v supply can be used to improve programming efficiency. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. when reprogramming data in a portion of memory already programmed (changing programmed data from '0' to '1') operation failure can be detected by a logical or be- tween the previous and the current value. enhanced buffered program abort reset command after an enhanced buffered program command is aborted, the device will ac- cept only an enhanced buffered program abort reset (f0h) command. this command resets the device following the aborted command and before the next com- mand can be executed. when this command completes and the device is reset, the memory waits for either an enhanced buffered program command or an exit enhanced buffered program command. the enhanced buffered programming sequence can be aborted in the following ways: ? write to an address in a different block than the one specified during the enhanced buffered program load command. ? write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. ? load address/data pairs in an incorrect sequence during the enhanced buffered pro- gram. ? load a number of data that is less or greater than 256 during the program step. the abort condition is indicated by dq1 = 1, dq6 = toggle, and dq5 = 0 (all of which are status register bits). a buffered program abort and reset command sequence must be written to reset the device for the next operation. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 10: enhanced buffered program flowchart enhanced buffered program command set start read dq5 & dq6 at valid address dq6 = toggle dq5 =1 read dq6 twice at valid address dq6 = toggle fail read dq6 at valid address read status register (dq1, dq5, dq7) at last loaded address dq7 = data check status register (dq5, dq7) at last loaded address dq5 = 1 dq7 = data (3) enhanced buffered program confirm, block address fail or abort (4) 258 th write cycle of the enhanced buffered program command end new program? exit enhanced buffered program command set yes yes yes yes yes yes yes no no no dq1 = 1 yes no no no no no x = x-1 write buffer data, start address (00), x=255 x = 0 no abort write to buffer write next data, (2) program address pair yes write to a different block address enhanced buffered program aborted (1) enhanced buffered program command, block address write next data, (2) program address pair first cycle of the enhanced buffered program command yes no 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. notes: 1. the enhanced buffered program abort reset command must be issued to return the device to read mode. 2. when the block address is specified, all addresses in the selected block address space must be issued starting from 00h. furthermore, when loading the write buffer address with data, data program addresses must be consecutive. 3. dq7 must be checked since dq5 and dq7 may change simultaneously. 4. if this flowchart location is reached because dq5 = 1, then the enhanced buffered program command failed. if this flowchart location is reached because dq1 = 1, then the enhanced buffered program command aborted. in both cases, the appropriate reset command must be issued to return the device to read mode: a reset command if the operation failed; an enhanced buffered program abort reset command if the operation aborted. exit enhanced buffered program command the exit enhanced buffered program command requires two bus write cycles and is used to return the device to read mode. until this command is issued, only the enhanced buffered program command can be issued, and all other commands are ignored. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. erase operations chip erase command the chip erase (80/10h) command erases the entire chip. six bus write operations are required to issue the command and start the program/erase controller. protected blocks are not erased. if all blocks are protected, the chip erase operation appears to start, but will terminate within approximately100 s, leaving the data un- changed. no error is reported when protected blocks are not erased. during the chip erase operation, the device ignores all other commands, including erase suspend. it is not possible to abort the operation. all bus read operations dur- ing chip erase output the status register on the data i/os. see the status register sec- tion for more details. after the chip erase operation completes, the device returns to read mode, unless an error has occurred. if an error occurs, the device will continue to output the status regis- ter. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the device to 1. all previous data is lost. the operation is aborted by performing a reset or by powering-down the device. in this case, data integrity cannot be ensured, and it is recommended that the entire chip be erased again. unlock bypass chip erase command when the device is in unlock bypass mode, the unlock bypass chip erase (80/10h) command can be used to erase all memory blocks at one time. the command requires only two bus write operations instead of six using the standard chip erase com- mand. the final bus write operation starts the program/erase controller. the unlock bypass chip erase command behaves the same way as the chip erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. block erase command the block erase (80/30h) command erases a list of one or more blocks. it sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. six bus write operations are required to select the first block in the list. each addition- al block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. after the command sequence is written, a block erase timeout occurs. during the timeout period, additional block addresses and block erase commands can be written. after the program/erase controller has started, it is not possible to select any more blocks. therefore, each additional block must be selec- ted within the timeout period of the last block. the timeout timer restarts when an ad- ditional block is selected. after the sixth bus write operation, a bus read operation outputs the status register. bus read operations from banks different from those that include the blocks being erased output the memory array content. see the we#-con- 256mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. trolled program waveforms for details on how to identify if the program/erase controller has started the block erase operation. after the block erase operation completes, the device returns to read mode, unless an error has occurred. if an error occurs, bus read operations will continue to output the status register. a read/reset command must be issued to reset the error condi- tion and return to read mode. if any selected blocks are protected, they are ignored, and all the other selected blocks are erased. if all of the selected blocks are protected, the block erase operation ap- pears to start, but will terminate within approximately100 s, leaving the data un- changed. no error condition is given when protected blocks are not erased. during the block erase operation, the device ignores all commands except the erase suspend command and the read/reset command, which is accepted only during the timeout period. the operation is aborted by performing a reset or powering- down the device. in this case, data integrity cannot be ensured, and it is recommended that the aborted blocks be erased again. unlock bypass block erase command when the device is in unlock bypass mode, the unlock bypass block erase (80/30h) command can be used to erase one or more memory blocks at a time. the command requires two bus write operations instead of six using the standard block erase command. the final bus write operation latches the address of the block and starts the program/erase controller. to erase multiple blocks (after the first two bus write operations have selected the first block in the list), each additional block in the list can be selected by repeating the sec- ond bus write operation using the address of the additional block. the unlock bypass block erase command behaves the same way as the block erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. bus read operations from banks different from those that include the blocks being erased output the memory array content. see the block erase command section for details. erase suspend command the erase suspend (b0h) command temporarily suspends a block erase opera- tion. one bus write operation with the block address is required to issue the com- mand. after the command sequence is written, a minimum block erase timeout occurs. during the timeout period, additional block addresses and block erase commands can be writ- ten. the program/erase controller suspends the erase operation within the erase suspend latency time of the erase suspend command being issued. however, when the erase suspend command is written during the block erase timeout, the device im- mediately terminates the timeout period and suspends the erase operation. after the program/erase controller has stopped, the device operates in read mode, and the erase is suspended. during an erase suspend operation, it is possible to read and execute program op- erations or write to buffer program operations in blocks that are not suspended. 256mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. both read and program operations behave normally on these blocks. reading from blocks that are suspended will output the status register. if any attempt is made to pro- gram in a protected block or in the suspended block, the program command is ignor- ed, and the data remains unchanged. in this case, the status register is not read, and no error condition is given. it is also possible to issue the auto select command after entering auto select mode. the read/reset command must be issued to return the device to read array mode be- fore the erase resume command will be accepted. during an erase suspend operation and after the enter extended memory block command is issued, a bus read operation to the extended memory block will output the extended memory block data. after the device enters extended memory block mode, the exit extended memory block command must be issued before the erase operation can be resumed. an erase suspend command is ignored if it is written during a chip erase opera- tion. if the erase suspend operation is aborted by performing a device reset or power- down, data integrity cannot be ensured, and it is recommended that the suspended blocks be erased again. erase resume command the erase resume (30h) command restarts the program/erase controller after an erase suspend operation. the device must be in read array mode before the erase resume command will be accepted. an erase can be suspended and resumed more than once. 256mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. block protection command definitions C address-data cycles table 17: block protection command definitions C address-data cycles, 16-bit notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d lock register commands enter lock register command set (40h) x16 555 aa 2aa 55 555 40 3 program lock register (a0h) x16 x a0 x data 5 read lock register x16 x data 4, 5, 6 password protection commands enter password protection command set (60h) x16 555 aa 2aa 55 555 60 3 program password (a0h) x16 x a0 pwan pwdn 7 read password x16 00 pwd0 01 pwd1 02 pwd2 03 pwd3 4, 6, 8 unlock password (25h/03) x16 00 25 00 03 00 pwd0 01 pwd1 00 29 8 nonvolatile protection commands enter nonvolatile protection command set (c0h) x16 555 aa 2aa 55 (bka) bad c0 3 program nonvolatile protection bit (a0h) x16 x a0 (bka) bad 00 read nonvolatile protection bit status x16 (bka) bad read(0) 4, 6, 10 clear all nonvolatile protection bits (80/30h) x16 x 80 00 30 11 nonvolatile protection bit lock bit commands enter nonvolatile protection bit lock bit command set (50h) x16 555 aa 2aa 55 555 50 3 program nonvolatile protection bit lock bit (a0h) x16 x a0 x 00 10 read nonvolatile protection bit lock bit status x16 (bka) read(0) 4, 6, 10 volatile protection commands 256mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 17: block protection command definitions C address-data cycles, 16-bit (continued) notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d enter volatile protection command set (e0h) x16 555 aa 2aa 55 (bka) 555 e0 3 program volatile protection bit (a0h) x16 x a0 (bka) bad 00 read volatile protection bit status x16 (bka) bad read(0) 4, 6, 10 clear volatile protection bit (a0h) x16 x a0 (bka) bad 01 extended memory block commands enter extended memory block (88h) x16 555 aa 2aa 55 555 88 3 read extended memory block x16 bad rd program extended memory block x16 x a0 bad pd exit extended memory block (90/00h) x16 555 aa 2aa 55 555 90 x 00 exit protection commands exit protection command set (90/00h) x16 x 90 x 00 3 notes: 1. key: a = address and d = data; x = "dont care;" bad = any address in the block; bka = bank address; pwdn = password bytes 0 to 7; pwan = password address, n = 0 to 7; rd(0) = dq0 protection indicator bit; if protected, dq0 = 00h, while if unprotected, dq0 = 01h. gray = not applicable. all values in the table are hexadecimal. 2. dq[15:8] are "dont care" during unlock and command cycles. a[max:16] are "dont care" during unlock and command cycles, unless an address is required. 3. the enter command sequence must be issued prior to any operation. it disables read and write operations from and to block 0. read and write operations from and to any other block are allowed. also, when an enter command set command is issued, an exit protection command set command must be issued to return the device to read mode. 4. read register/password commands have no command code; ce# and oe# are driven low and data is read according to a specified address. 5. data = lock register content. 6. all address cycles shown for this command are read cycles. 7. only one portion of the password can be programmed by each program password command. 8. each portion of the password can be entered or read in any order as long as the entire 64-bit password is entered or read. 9. for the x16 unlock password command, the n th (and final) address cycle equals the 7th address cycle. for the 5th and 6th address cycles, the values for the address and data 256mb: 3v embedded parallel nor flash block protection command definitions C address-data cycles pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3. 10. both nonvolatile and volatile protection bit settings are as follows: protected state = 00; unprotected state= 01. 11. the clear all nonvolatile protection bits command programs all nonvolatile pro- tection bits before erasure. this prevents over-erasure of previously cleared nonvolatile protection bits. protection operations blocks can be protected individually against accidental program and erase opera- tions. the block protection scheme is shown in the software protection scheme figure. memory block and extended memory block protection is configured through the lock register. lock register commands the enter lock register command set (40h) requires three bus write cycles. af- ter it has been issued, all bus read or program operations can be issued to the lock register. the exit protection command set (90/00h) command must be used to exit the lock register ane return to read mode. the program lock register (a0h) command allows the lock register to be config- ured. the programmed data can then be checked with a read lock register com- mand by driving ce# and oe# low with the appropriate address data on the address bus. password protection commands after the enter password protection command set (60h) command has been issued, only commands related to password protection mode and the exit protec- tion command set command can be issued to the device. this command requires three bus write cycles. the exit protection command set command must be is- sued following all password protection commands to return the device to read mode. the program password (a0h) command is used to program the 64-bit password used in the password protection mode. to program the 64-bit password, the complete command sequence must be entered four times at four consecutive addresses selected by a[1:0] in 16-bit mode. this command must be used according to all program com- mand timings. command results can be verified by checking the status register. by de- fault, all password bits are set to 1. the password can be checked by issuing a read password command. the read password command is used to verify the password used in password pro- tection mode. to verify the 64-bit password, the complete command sequence must be entered four times at four consecutive addresses selected by a[1:0] in 16-bit mode. if the password mode lock bit is programmed and the user attempts to read the password, the device will output ffh onto the i/o data bus. the unlock password (25/03h) command is used to clear the nonvolatile protec- tion bit lock bit, allowing the nonvolatile protection bits to be modified. the unlock password command must be issued, along with the correct password, and requires a 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. 1 s delay between successive unlock password commands in order to prevent un- authorized intruders from retrieving the password by trying all possible 64-bit combi- nations. if this delay does not occur, the latest command will be ignored. approximately 1 s is required for unlocking the device after the valid 64-bit password has been provi- ded. nonvolatile protection commands after the enter nonvolatile protection command set (c0h) command has been issued, the commands related to nonvolatile protection mode can be issued to the device. this command requires three bus write cycles. a block can be protected from program or erase by issuing a program nonvolatile protection bit (a0h) command, along with the block address. this command sets the nonvolatile protection bit to 0 for a given block. this command must be used ac- cording to all program command timings. command results can be verified by checking the status register. the status of a nonvolatile protection bit for a given block or group of blocks can be read by issuing a read nonvolatile modify protection bit command, along with the block address. the nonvolatile protection bits are erased simultaneously by issuing a clear all nonvolatile protection bits (80/30h) command. no specific block address is re- quired. if the nonvolatile protection bit lock bit is set to 0, the command fails. 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 11: program/erase nonvolatile protection bit algorithm no no yes yes dq6 = toggle enter nonvolatile protection command set start program nonvolatile protection bit addr = bad fail read byte twice addr = bad read byte twice addr = bad no no yes yes dq6 = toggle reset dq5 = 1 exit protection command set dq0 = 1 (erase) 0 (program) read byte twice addr = bad wait 500s pass nonvolatile protection bit lock bit commands after the enter nonvolatile protection bit lock bit command set (50h) command has been issued, the commands that allow the nonvolatile protection bit lock bit to be set can be issued to the device. this command requires three bus write cycles. the program nonvolatile protection bit lock bit (a0h) command is used to set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection bits and preventing them from being modified. 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. the read nonvolatile protection bit lock bit status command is used to read the status of the nonvolatile protection bit lock bit. volatile protection commands after the enter volatile protection command set (e0h) command has been issued, commands related to the volatile protection mode can be issued to the device. this command requires three bus write cycles. the program volatile protection bit (a0h) command individually sets a vola- tile protection bit to 0 for a given block. if the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (see the block protection status table.) the status of a volatile protection bit for a given block can be read by issuing a read volatile protection bit status command along with the block address. the clear volatile protection bit (a0h) command individually clears (sets to 1) the volatile protection bit for a given block. if the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (see the block protection status table.) extended memory block commands the device has one extra 256-word block (extended memory block) that can only be ac- cessed by the enter extended memory block command when the device is in ex- tended block mode. the device can be shipped with the extended memory block pre- locked permanently by micron, or with the extended memory block unlocked, enabling customers to permanently program and lock it. (see lock register, the auto select command, and the block protection table.) the extended memory block is used as a security block (to provide a permanent securi- ty identification number) or to store additional information. the extended memory block is divided in two memory areas of 128 words each: the first area is factory locked and the second one is customer lockable. it is perma- nently protected from program operations and cannot be unprotected. the random number, electronic serial number (esn) and security identification number are written in this section in the factory. the second area is customer lockable. it is up to the customer to protect it from pro- gram operations. its status is indicated by bit dq6 and dq7. when dq7 is set to 1 and dq6 to 0, it indicates that this second memory area is customer lockable. when dq7 and dq6 are both set to 1, it indicates that the second part of the extended memory block is customer locked and protected from program operations. bits dq6 and dq7 are the most significant bits in the extended block protection indicator and a specific procedure must be followed to read it. table 18: extended memory block address and data address data micron prelocked customer lockable 000000hC00007fh secure id number unavailable 000080h-0000ffh unavailable determined by customer 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. three bus write cycles are required to issue the extended memory block command. once the command has been issued the device enters the extended memory block mode where all bus read or program operations are conducted on the extended memo- ry block. once the device is in the extended block mode, the extended memory block is addressed by using the addresses occupied by block 0 in the other operating modes (see the memory map table). the device remains in extended memory block mode until the exit extended mem- ory block command is issued or power is removed from the device. after power-up or hardware reset, the device reverts to read mode where the commands issued to the block 0 address space will properly address block 0. the extended memory block cannot be erased, and can be treated as one-time pro- grammable (otp) memory. in extended block mode, erase, chip erase, erase suspend and erase resume com- mands are not allowed. to exit from the extended memory block mode the exit extended memory block command must be issued. this command requires four bus write cycles. the extended memory block can be protected by setting the extended memory block protection bit to 0 (see lock register); however once protected the protection cannot be undone. note: when the device is in the extended memory block mode, the vpp/wp pin cannot be used for fast programming and the unlock bypass mode is not available (see v pp // wp). exit protection command the exit protection command set (90/00h) command is used to exit the lock register, password protection, nonvolatile protection, volatile protection, and nonvola- tile protection bit lock bit command set modes and return the device to read mode. 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. device protection hardware protection the v pp /wp# function provides a hardware method of protecting the four outermost blocks; that is, the two 32-kword blocks at the top and the two 32-kword blocks at the bottom of the address space. when v pp /wp# is low, program and erase operations on the four outermost blocks are ignored to provide protection. when v pp /wp# is high, the device reverts to the previous protection status for these four outermost blocks. program and erase operations can modify the data in these blocks unless the blocks are protected using block protection. when v pp /wp# is raised to vpph, the device automatically enters the unlock bypass mode, and command execution time is faster. this must never be done from any mode except read mode; otherwise the device might be left in an indeterminate state. a 0.1 f capacitor should be connected between the v pp /wp# pin and the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program. when v pp /wp# returns to high or low, normal operation resumes. when operations execute in unlock bypass mode, the device draws ipp from the pin to supply the pro- gramming circuits. transitions from high to vpph and from vpph to low must be slower than t vhvpp . note: micron highly recommends driving v pp /wp# high or low. if a system needs to float the v pp /wp# pin, without a pull-up/pull-down resistor and no capacitor, then an internal pull-up resistor is enabled. table 19: v pp /wp# functions v pp /wp# settings function v il four outermost parameter blocks (first two and last two) protected from program or erase operations. v ih four outermost parameter blocks (first two and last two) unprotected from program or erase operations, unless a software activated protection is in place. v pph unlock bypass mode supplies current necessary to speed up program execution time. software protection the following software protection modes are available: ? volatile protection ? nonvolatile protection ? password protection the device is shipped with all blocks unprotected. on first use, the device defaults to the nonvolatile protection mode but can be activated in either the nonvolatile protec- tion or password protection mode. the desired protection mode is activated by setting either the nonvolatile protection mode lock bit or the password protection mode lock bit of the lock register (see the lock register section). both bits are one-time-programmable and nonvolatile; therefore, af- ter the protection mode has been activated, it cannot be changed, and the device is set 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. permanently to operate in the selected protection mode. it is recommended that the desired software protection mode be activated when first programming the device. for the four outermost blocks (that is the two blocks at the top and the two at the bot- tom of the address space), an even higher level of block protection can be achieved by locking the blocks using the non-volatile protection and then by holding v pp /wp# low. blocks with volatile protection and nonvolatile protection can coexist within the memo- ry array. if the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. the block protection status can be read by performing a read electronic signature or by issuing an auto select command (see the block protection table). refer to the block protection status table and the software protection scheme figure for details on the block protection scheme. refer to the protection operations section for a description of the command sets. volatile protection mode volatile protection enables the software application to protect blocks against inadver- tent change and can be disabled when changes are needed. volatile protection bits are unique for each block and can be individually modified. volatile protection bits control the protection scheme only for unprotected blocks whose nonvolatile protection bits are cleared to 1. issuing a program volatile protection bit or clear volatile protection bit command sets to 0 or clears to 1 the volatile protection bits and places the associ- ated blocks in the protected (0) or unprotected (1) state, respectively. the volatile pro- tection bit can be set or cleared as often as needed. the default values of the volatile protections are set through the volatile lock boot bit of the lock register (see the lock register section). when the parts are first shipped, or after a power-up or hardware reset, the volatile pro- tection bits can be set or cleared depending upon the ordering option chosen: if the op- tion to clear the volatile protection bits after power-up is selected, then the blocks can be programmed or erased depending on the nonvolatile protection bits state (see the block protection status table); if the option to set the volatile protection bits after pow- er-up is selected, the blocks default to be protected (refer also to the protection com- mands). nonvolatile protection mode a nonvolatile protection bit is assigned to each block. each of these bits can be set for protection individually by issuing a program nonvolatile protection bit com- mand. also, each device has one global volatile bit called the nonvolatile protection bit lock bit; it can be set to protect all nonvolatile protection bits at once. this global bit must be set to 0 only after all nonvolatile protection bits are configured to the desired settings. when set to 0, the nonvolatile protection bit lock bit prevents changes to the state of the nonvolatile protection bits. when cleared to 1, the nonvolatile protection bits can be set and cleared using the program nonvolatile protection bit and clear all nonvolatile protection bits commands, respectively. no software command unlocks the nonvolatile protection bit lock bit unless the device is in password protection mode; in nonvolatile protection mode, the nonvolatile protec- 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. tion bit lock bit can be cleared only by taking the device through a hardware reset or power-up. nonvolatile protection bits cannot be cleared individually; they must be cleared all at once using a clear all nonvolatile protection bits command. they will re- main set through a hardware reset or a power-down/power-up sequence. if one of the nonvolatile protection bits needs to be cleared (unprotected), additional steps are required: first, the nonvolatile protection bit lock bit must be cleared to 1, us- ing either a power-cycle or hardware reset. then, the nonvolatile protection bits can be changed to reflect the desired settings. finally, the nonvolatile protection bit lock bit must be set to 0 to lock the nonvolatile protection bits. the device now will operate nor- mally. to achieve the best protection, the program nonvolatile protection lock bit command should be executed early in the boot code, and the boot code should be pro- tected by holding v pp /wp# low. nonvolatile protection bits and volatile protection bits have the same function when v pp /wp# is high or when v pp /wp# is at the voltage for program acceleration (v pph ). password protection mode password protection mode provides a higher level of security than the nonvolatile pro- tection mode by requiring a 64-bit password to unlock the nonvolatile protection bit lock bit. in addition to this password requirement, the nonvolatile protection bit lock bit is set to 0 after power-up and reset to maintain the device in password protection mode. executing the unlock password command by entering the correct password clears the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to be modified. if the password provided is incorrect, the nonvolatile protection bit lock bit remains locked, and the state of the nonvolatile protection bits cannot be modified. to place the device in password protection mode, the following two steps are required: first, before activating the password protection mode, a 64-bit password must be set and the setting verified. password verification is allowed only before the password pro- tection mode is activated. next, password protection mode is activated by program- ming the password protection mode lock bit to 0. this operation is irreversible; after the bit is programmed, it cannot be erased. the device remains permanently in password protection mode, and the 64-bit password can be neither retrieved nor reprogrammed. in addition, all commands to the address where the password is stored are disabled. note: there is no means to verify the password after password protection mode is ena- bled. if the password is lost after enabling the password protection mode, there is no way to clear the nonvolatile protection bit lock bit. nvpbs default to 1 (block unprotected) after power-up and hardware reset. a block is protected or unprotected when its nvpb is set to 0 and 1, respectively. nvpbs are programmed individually and cleared collectively. vpb default status depends on ordering option. a block is protected or unprotected when its vpb is set to 0 and 1, respectively. vpbs are programmed and cleared indi- vidually. for the volatile protection to be effective, the nvpb lock bit must be set to 0 (nvpb bits unlocked) and the block nvpb must be set to 1 (block unprotected). 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. 3. the nvpb lock bit is volatile and default to 1 (nvpb bits unlocked) after power-up and hardware reset. nvpb bits are locked by setting the nvpb lock bit to 0. once pro- grammed to 0, the nvpb lock bit can be reset to 1 only be taking the device through a power-up or hardware reset. figure 12: software protection scheme 1 = unprotected (default) 0 = protected 1 = unprotected 0 = protected (default setting depends on the product order option) volatile protection bit nonvolatile protection bit 1 = unlocked (default, after power-up or hardware reset) 0 = locked nonvolatile protection bit lock bit (volatile) nonvolatile protection mode password protection mode volatile protection nonvolatile protection array block notes: 1. nonvolatile protection bits default to 1 (block unprotected) when the parts are first shipped. a block is protected or unprotected when its nonvolatile protection bit is set to 0 and 1, respectively. 2. volatile protection bits are programmed and cleared individually. nonvolatile protection bits are programmed individually and cleared collectively. 3. volatile protection bit default status depends on ordering option. a block is protected or unprotected when its volatile protection bit is set to 0 and 1, respectively. for the vol- atile protection to be effective, the block nonvolatile protection bit must be set to 1 (block unprotected). 4. once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by taking the device through a power-up or hardware reset. 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. dual operations and multiple bank architecture the multiple bank architecture gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual operations feature simpli- fies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency. only one bank at a time is allowed to be in program or erase mode. however, certain commands can cross bank boundaries, which means that during an operation only the banks that are not concerned with the cross bank operation are available for dual oper- ations. for example, if a block erase command is issued to erase blocks in both bank a and bank b, then only banks c or d are available for read operations while the erase is being executed. if a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one program- ming and other banks in read mode. by using a combination of these features, read operations are possible at any moment. the tables below show the dual operations possible in other banks and in the same bank. note that only the commonly used commands are represented in these tables. table 20: dual operations allowed in other banks status of bank commands allowed in another bank read read status register 2 read cfi query auto select program erase program/erase suspend program/erase resume idle yes yes 3 yes yes yes yes yes 3 yes 4 programming yes no no no C C no no erasing yes no no no C C no no program suspended yes no no yes no no C no erase suspended yes no no yes yes no C yes 5 notes: 1. if several banks are involved in a program or erase operation, then only the banks that are not concerned with the operation are available for dual operations. 2. read status register is not a command. the status register can be read during a block program or erase operation. 3. only after a program or erase operation in that bank. 4. only after a program or erase suspend command in that bank. 5. only an erase resume is allowed if the bank was previously in erase suspend mode. 256mb: 3v embedded parallel nor flash dual operations and multiple bank architecture pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 21: dual operations allowed in same bank status of bank commands allowed in same bank read read status register 1 read cfi query auto select program erase program/erase suspend program/erase resume idle yes yes yes yes yes yes yes 2 yes 3 programming no yes no no C C yes 4 C erasing no yes no no C no yes 5 C program suspended yes no no yes no C C yes erase suspended yes 6 yes 7 no yes yes 6 no C yes notes: 1. read status register is not a command. the status register can be read during a block program or erase operation. 2. only after a program or erase operation in that bank. 3. only after a program or erase suspend command in that bank. 4. only a program suspend. 5. only an erase suspend. 6. not allowed in the block or word that is being erased or programmed. 7. the status register can be read by addressing the block being erase suspended. 256mb: 3v embedded parallel nor flash dual operations and multiple bank architecture pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. common flash interface the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued, the memory enters read cfi query mode and read operations output the cfi data. the tables here show the addresses (a0-a7) used to retrieve the data. the cfi data structure also contains a security area where a 64-bit unique security number is written (see table 40: security code area). this area can be accessed only in read mode by the final user. it is impossible to change the se- curity number after it has been written by micron. table 22: query structure overview note applies to the entire table. address sub-section name description x16 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing & voltage information 27h device geometry definition flash device layout 40h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h security code area 64-bit unique device number note: 1. query data are always presented on the lowest order data outputs. table 23: cfi query identification string note applies to the entire table. address data description value x16 10h 0051h q 11h 0052h query unique ascii string qry r 12h 0059h y 13h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm spansion compatible 14h 0000h 15h 0040h address for primary algorithm extended query table (see the primary algorithm-specific extended query table) p = 40h 16h 0000h 17h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 0000h 19h 0000h address for alternate algorithm extended query table na 1ah 0000h note: 1. query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are 0. 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 24: cfi query system interface information note applies to the entire table. address data description value x16 1bh 0027h v cc logic supply minimum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 2.7 v 1ch 0036h v cc logic supply maximum program/erase voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 mv 3.6 v 1dh 0085h v pph [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 8.5 v 1eh 0095h v pph [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9.5 v 1fh 0004h typical timeout for single word program = 2 n s 16 s 20h 0004h typical timeout for minimum size write buffer program = 2 n s 16 s 21h 0009h typical timeout for individual block erase = 2 n ms 0.5 s 22h 0011h typical timeout for full chip erase = 2 n ms 80 s 23h 0004h maximum timeout for word program = 2 n times typical 200 s 24h 0004h maximum timeout for write buffer program = 2 n times typical 200 s 25h 0003h maximum timeout per individual block erase = 2 n times typical 2.3 s 26h 0004h maximum timeout for chip erase = 2 n times typical 800 s note: 1. the values given in the above table are valid for both packages. table 25: device geometry definition address data description value x16 27h 0019h device size = 2 n in number of bytes 32 mbytes 28h 29h 0001h 0000h flash device interface code description x16 async. 2ah 2bh 0006h 0000h maximum number of bytes in multiple-byte program or page= 2 n 64 2ch 0003h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 3 2dh 2eh 2fh 30h 0003h 0000h 0000h 0001h erase block region 1 information 2dh-2eh: number of erase blocks of identical size 2fh-30h: block size (n*256 bytes) 4 blocks, 32-kwords 31h 32h 33h 34h 007dh 0000h 0000h 0004h erase block region 2 information 126 blocks, 128-kwords 35h 36h 37h 38h 0003h 0000h 0000h 0001h erase block region 3 information 4 blocks, 32-kwords 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information na 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 26: primary algorithm-specific extended query table address data description value x16 40h 0050h primary algorithm extended query table unique ascii string pri p 41h 0052h r 42h 0049h i 43h 0031h major version number, ascii 1 44h 0033h minor version number, ascii 3 45h 0010h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) yes 65 nm 46h 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 0001h block protection 00 = not supported, x = number of blocks per group 1 48h 0000h temporary block unprotect 00 = not supported, 01 = supported not supported 49h 0008h block protect /unprotect 08 = M29DW256G 8 4ah 0073h simultaneous operations: x= block number (excluding bank a) 115 4bh 0000h burst mode, 00 = not supported, 01 = supported not supported 4ch 0002h page mode, 00 = not supported, 02 = 8-word page 02 4dh 0085h v pph supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 8.5 v 4eh 0095h v pph supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9.5 v 4fh 0001h 01 = dual boot dual boot 50h 0001h program suspend, 00 = not supported, 01 = supported supported 51h 0001h unlock bypass: 00 = not supported, 01 = supported supported 52h 0008h extended memory block size (customer lockable), 2 n bytes 256 57h 0004h bank organization, 00 = data at 4ah is 0, x= bank number 4 58h 0013h bank a information, x = number of blocks in bank a 19 59h 0030h bank b information, x = number of blocks in bank b 48 5ah 0030h bank c information, x = number of blocks in bank c 48 5bh 0013h bank d information, x = number of blocks in bank d 19 note: 1. the values given in the above table are valid for both packages. table 27: security code area address data description x16 61h xxxx 64-bit: unique device number 62h xxxx 63h xxxx 64h xxxx 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. power-up and reset characteristics table 28: power-up wait timing specifications note 1 applies to the entire table parameter symbol min max unit notes legacy jedec v cc high to ce# low t vch t vchel 55 C s 2 v ccq high to ce# low C t vcqhel 55 C s 2 v cc high to we# low C t vchwl 500 C s v ccq high to we# low C t vcqhwl 500 C s notes: 1. specifications apply to 70 and 80ns devices unless otherwise noted. 2. v cc and v ccq ramps must be synchronized during power-up. figure 13: power-up timing v cc t vcqhel ce# v ccq t vcqhwl we# t vchel t vchwl 256mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 29: reset ac specifications note 1 applies to the entire table condition/parameter symbol min max unit notes legacy jedec rst# low to read mode during program or erase t ready t plrh C 55 s 2 rst# pulse width t rp t plph 20 C s rst# high to ce# low, oe# low t rh t phel, t phgl, t phwl 55 C ns 2 rst# low to standby mode during read mode t rpd C 20 C s rst# low to standby mode during program or erase 55 C s ry/by# high to ce# low, oe# low t rb t rhel, t rhgl, t rhwl 0 C ns 2 notes: 1. specifications apply to 70 and 80ns devices unless otherwise noted. 2. sampled only; not 100% tested. figure 14: reset ac timing C no program/erase operation in progress t rh ry/by# ce#, oe#, we# rst# t rp figure 15: reset ac timing during program/erase operation t rb ry/by# ce#, oe#, we# rst# t rp t rh t ready 256mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. absolute ratings and operating conditions stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. table 30: absolute maximum/minimum ratings parameter symbol min max unit notes temperature under bias t bias C50 125 c storage temperature t stg C65 150 c input/output voltage v io C0.6 v cc + 0.6 v 1, 2 supply voltage v cc C0.6 4 v input/output supply voltage v ccq C0.6 4 v program voltage v pph C0.6 10.5 v 3 notes: 1. during signal transitions, minimum voltage may undershoot to ?2v for periods less than 20ns. 2. during signal transitions, maximum voltage may overshoot to v cc + 2v for periods less than 20ns. 3. v pph must not remain at 9v for more than 80 hours cumulative. table 31: operating conditions parameter symbol 70ns 80ns unit min max min max supply voltage v cc 2.7 3.6 2.7 3.6 v input/output supply voltage (v ccq v cc ) v ccq 2.7 3.6 1.65 3.6 v ambient operating temperature (range 1) t a 0 70 0 70 c ambient operating temperature (range 6) t a C40 85 C40 85 c load capacitance c l 30 30 pf input rise and fall times C C 10 C 10 ns input pulse voltages C 0 to v ccq 0 to v ccq v input and output timing reference vol- tages C v ccq /2 v ccq /2 v 256mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 16: ac measurement load circuit c l v ccq 25k device under test 0.1f v cc 0.1f v pp 25k note: 1. c l includes jig capacitance. figure 17: ac measurement i/o waveform v ccq 0v v ccq /2 table 32: input/output capacitance 1 parameter symbol test condition min max unit input capacitance c in v in = 0v C 6 pf output capacitance c out v out = 0v C 12 pf note: 1. sampled only, not 100% tested. 256mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. dc characteristics table 33: dc current characteristics parameter symbol conditions min typ max unit notes input leakage current i li 0v v in v cc C C 1 a 1 output leakage current i lo 0v v out v cc C C 1 a vcc read current random read i cc1 ce# = v il , oe# = v ih , f = 6 mhz C C 10 ma page read ce# = v il , oe# = v ih , f = 10 mhz C C 1 ma vcc standby current i cc2 ce# = v ccq 0.2v, rst# = v ccq 0.2v C C 100 a vcc program/erase current i cc3 program/ erase controller active v pp /wp# = v il or v ih C C 20 ma 2 v pp /wp# = v pph C C 15 ma v pp current read i pp1 v pp /wp# v cc C 1 5 a standby C 1 5 a reset i pp2 rst# = v ss 0.2v C 1 5 a program operation ongoing i pp3 v pp /wp# = 12v 5% C 1 10 ma v pp /wp# = v cc C 1 5 ma erase operation ongoing i pp4 v pp /wp# = 12v 5% C 3 10 ma v pp /wp# = v cc C 1 5 ma notes: 1. the maximum input leakage current is 5a on the v pp /wp# pin. 2. sampled only; not 100% tested. table 34: dc voltage characteristics parameter symbol conditions min typ max unit notes input low voltage v il v cc 2.7v C0.5 C 0.3v ccq v input high voltage v ih v cc 2.7v 0.7v ccq C v ccq + 0.4 v output low voltage v ol i ol = 100a, v cc = v cc,min , v ccq = v ccq,min C C 0.15v ccq v output high voltage v oh i oh = 100a, v cc = v cc,min , v ccq = v ccq,min 0.85v ccq C C v voltage for v pp /wp# program acceleration v pph C C 8.5 9.5 v program/erase lockout supply voltage v lko C 1.8 C 2.5 v 1 note: 1. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. read ac characteristics table 35: read ac characteristics parameter symbol condition 70ns v ccq = v cc 80ns v ccq = 1.65v to v cc unit notes min max min max legacy jedec address valid to next address valid t rc t avav ce# = v il , oe# = v il 70 C 80 C ns address valid to output valid t acc t avqv ce# = v il , oe# = v il C 70 C 80 ns address valid to output valid (page) t page t avqv1 ce# = v il , oe# = v il C 25 C 30 ns ce# low to output transition t lz t elqx oe# = v il 0 C 0 C ns 1 ce# low to output valid t e t elqv oe# = v il C 70 C 80 ns oe# low to output transition t olz t glqx ce# = v il 0 C 0 C ns 1 oe# low to output valid t oe t glqv ce# = v il C 25 C 30 ns ce# high to output high-z t hz t ehqz oe# = v il C 25 C 30 ns 1 oe# high to output high-z t df t ghqz ce# = v il C 25 C 30 ns 1 ce#, oe#, or address transition to output transition t oh t ehqx, t ghqx, t axqx C 0 C 0 C ns note: 1. sampled only; not 100% tested. figure 18: random read ac timing valid valid t acc t rc t oh t e t lz t oh t hz t olz t oh t oe t df a[max:0] ce# oe# dq[15:0] 256mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 19: page read ac timing tghqx valid a[23:3] oe# dq[15:0] ce# telqv tehqx tghqz valid a[2:0] valid valid valid valid valid valid valid ta vqv ta vqv1 valid valid valid valid valid valid valid valid tglqv tehqz 256mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. write ac characteristics table 36: we#-controlled write ac characteristics parameter symbol 70ns v ccq = v cc 80ns v ccq = 1.65v to v cc unit notes legacy jedec min max min max address valid to next address valid t wc t avav 70 C 80 C ns ce# low to we# low t cs t elwl 0 C 0 C ns we# low to we# high t wp t wlwh 35 C 35 C ns input valid to we# high t ds t dvwh 45 C 45 C ns we# high to input transition t dh t whdx 0 C 0 C ns we# high to ce# high t ch t wheh 0 C 0 C ns we# high to we# low t wph t whwl 30 C 30 C ns address valid to we# low t as t avwl 0 C 0 C ns we# low to address transition t ah t wlax 45 C 45 C ns oe# high to we# low C t ghwl 0 C 0 C ns we# high to oe# low t oeh t whgl 0 C 0 C ns program/erase valid to ry/by# low t busy t whrl C 30 C 30 ns 1 v cc high to ce# low t vcs t vchel 50 C 50 C s note: 1. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 20: we#-controlled program ac timing 555h pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t df t whwh1 t wph t ah t e t cs t ghwl t oe t dh t oh t ch a[max:0] ce# oe# we# dq[15:0] aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. table 37: ce#-controlled write ac characteristics parameter symbol 70ns v ccq = v cc 80ns v ccq = 1.65v to v cc unit legacy jedec min max min max address valid to next address valid t wc t avav 75 C 85 C ns we# low to ce# low t ws t wlel 0 C 0 C ns ce# low to ce# high t cp t eleh 35 C 35 C ns input valid to ce# high t ds t dveh 45 C 45 C ns ce# high to input transition t dh t ehdx 0 C 0 C ns ce# high to we# high t wh t ehwh 0 C 0 C ns ce# high to ce# low t cph t ehel 30 C 30 C ns address valid to ce# low t as t avel 0 C 0 C ns ce# low to address transition t ah t elax 45 C 45 C ns oe# high to ce# low C t ghel 0 C 0 C ns 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 21: ce#-controlled program ac timing 555h pa pa 3rd cycle read cycle 4th cycle data polling t wc t as t cp t df t oh t oe t e t wc t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0] we# oe# ce# dq[15:0] aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7 (see data polling bit [dq7]). 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. accelerated program, data polling/toggle ac characteristics table 38: accelerated program and data polling/data toggle ac characteristics note 1 applies to the entire table. parameter symbol min max unit legacy jedec v pp /wp# rising or falling time C t vhvpp 250 C ns address setup time to oe# low during toggle bit polling t aso t axgl 10 C ns address hold time from oe# during toggle bit polling t aht t ghax, t ehax 10 C ns ce# high during toggle bit polling t eph t ehel2 10 C ns output hold time during data and toggle bit polling t oeh t whgl2, t ghgl2 20 C ns program/erase valid to ry/by# low t busy t whrl C 30 ns note: 1. specifications apply to 70, and 80ns devices unless otherwise noted. figure 22: accelerated program ac timing t vhvpp t vhvpp v pph v il or v ih v pp /wp# 256mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 23: data polling ac timing dq7# data dq7# valid dq7 data output flag data output flag valid dq[6:0] data t hz/ t df t e t oe t ch t busy t oeh ce# oe# we# dq[6:0] dq7 ry/by# notes: 1. dq7 returns a valid data bit when the program or erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. figure 24: toggle/alternative toggle bit polling ac timing toggle toggle toggle data stop toggling output valid t busy t oeh t eph t oeh ce# we# oe# dq6/dq2 ry/by# t oeh t aht t aso t aht t dh t as a[max:0]/ aC1 t oe t e notes: 1. dq6 stops toggling when the program or erase command has completed. dq2 stops toggling when the chip erase or block erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. 256mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. program/erase characteristics table 39: program/erase characteristics notes 1 and 2 apply to the entire table parameter min typ max unit notes chip erase C 145 400 s 3 chip erase v pp /wp# = v pph C 125 400 s 3 block erase (128 kword) C 1 4 s 3, 4 block erase (32 kword) C 0.37 1.5 s erase suspend latency time C 25 45 s block erase timeout 50 C C s word program single-word program C 16 200 s 3 write to buffer program (32 words at-a-time) v pp /wp# = v pph C 50 200 s 3 v pp /wp# = v ih C 70 200 s 3 chip program (word by word) C 270 400 s 3 chip program (write to buffer program) C 25 200 s 3, 6 chip program (write to buffer program with v pp /wp# = v pph ) C 13 50 s 3, 5 chip program (enhanced buffered program) C 15 60 s 5 chip program (enhanced buffered program with v pp /wp# = v pp ) C 10 40 s 5 program suspend latency time C 5 15 s program/erase cycles (per block) 100,000 C C cycles data retention 20 C C years notes: 1. typical values measured at room temperature and nominal voltages and for not cycled devices. 2. typical and maximum values are sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. 4. block erase polling cycle time (see data polling ac waveforms figure). 5. intrinsic program timing, that means without the time required to execute the bus cy- cles to load the program commands. 256mb: 3v embedded parallel nor flash program/erase characteristics pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. package dimensions figure 25: 56-pin tsop C 14mm x 20mm see detail a 0.50 typ 14.00 0.10 1.20 max 18.40 0.10 20.00 0.20 1.00 0.05 0.10 0.05 0.22 0.05 detail a 0.50 0.10 3 typ/ 5 max 0.10 0.10 min/ 0.21 max pin #1 notes: 1. all dimensions are in millimeters. 2. for the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 256mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 26: 64-pin tbga C 10mm x 13mm ball "a1" 0.10 max 0.50 typ 1.00 typ 0.80 typ 1.20 max 1.50 typ 3.00 typ 0.50 typ 7.00 typ 7.00 typ 10.00 0.10 13.00 0.10 0.35 min/ 0.50 max 0.30 -0.10 +0.05 note: 1. all dimensions are in millimeters. 256mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. figure 27: 64-ball fortified bga C 11mm x 13mm seating plane 0.80 typ 0.15 max 13.00 0.10 0.60 0.05 1.00 typ 3.00 typ 7.00 typ 1.40 max ball a1 id 1.00 typ 2.00 typ 11.00 0.10 7.00 typ 0.50 typ 64x 8 7 6 5 4 3 2 1 0.48 0.05 a b c d e f g h note: 1. all dimensions are in millimeters. 256mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 77 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. revision history rev. a C 10/12 ? initial micron brand release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 256mb: 3v embedded parallel nor flash revision history pdf: 09005aef84ecabef m29dw_256g.pdf - rev. a 10/12 en 78 micron technology, inc. reserves the right to change products or specifications without notice. ? 2012 micron technology, inc. all rights reserved. |
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